(1) Field of the Invention
The invention relates to a method of fabricating silicon structures, and more particularly, to the formation of local interconnects of polycide between narrowly spaced features in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
In the art, polycide stacks, for example, tungsten silicide overlying polysilicon, are often used for constructing local interconnects between nodes in SRAM memory cells. Polycide provides a low resistivity conductive material with good mechanical and chemical resistance properties. By using polycide to form local interconnects, it is possible to provide the necessary connectivity for a memory cell while not using additional, and expensive, metal interconnect processes. As an example, the polycide interconnect can be used for the common V.sub.ss connections between metal-oxide-semiconductor (MOS) transistors in a four transistor SRAM cell via self-aligned contacts (SAC). In such application, it is necessary that the polycide layer exhibit a low sheet resistance. Therefore, the tungsten silicide component of the polycide layer must be formed sufficiently thick to achieve a low sheet resistance for the total film.
Referring to FIG. 1, a cross-section of a partially completed prior art SRAM memory cell in an integrated circuit is shown. Four transistor gates 14 are shown formed overlying a substrate 10. Each gate 14 is composed of a gate dielectric 18, a polysilicon electrode 22, an encapsulating dielectric 26, and sidewall spacers 30. Source and drain regions 32 are formed in the substrate 10. The transistors shown are conventional and very common in the art. The transistors are for m ed as narrowly spaced pairs. An interpoly layer 34, or IPL, overlies the transistors and substrate 10. The interpoly layer 34 is a dielectric material.
Referring now to FIG. 2, the interpoly layer 34 has been patterned. The opening in the interpoly layer 34 is for a contact to the source or drain region 32 between the narrowly spaced transistor gates 14. Note that the opening in the interpoly layer 34 is larger than the contact area at the surface of the substrate 10. Such a contact opening is called a self-aligned contact (SAC).
Referring now to FIG. 3, a polysilicon layer 38 and a metal silicide layer 42 are deposited overlying the interpoly layer 34 and the substrate 10 in the source or drain region 32. The metal silicide layer 42 is composed, for example, of tungsten silicide (WSi.sub.x). The combination of the polysilicon layer 38 and the metal silicide layer 42 forms a polycide layer.
Referring now to FIG. 4, the metal silicide layer 42 and the polysilicon layer 38 are patterned to form local interconnects out of polycide. In the etch process, the metal silicide layer 42 and the polysilicon layer 38 are removed where not protected by a mask that is not shown. It is crucial that all of the exposed polycide be removed during the etching step. Unfortunately, polycide is not easy to etch. In constricted areas, such as between the narrowly spaced gates 14, the polycide may not etch completely away. Polycide stringers 46 may remain following this etch. These polycide stringers 46 create potential shorting conditions for the circuit and are unacceptable.
This problem could be eliminated by depositing and planarizing a very thick interpoly layer. Unfortunately, this will create other problems in the etching process. overetching of the encapsulating layer or the sidewall spacers could occur due to the greater depth of the interpoly layer that would have to be etched through. Gate shorts to the local interconnect polycide would result.
Several prior art approaches disclose methods to form contacts and to utilize metal silicide in the fabrication of integrated circuits. U.S. Pat. No. 5,573,980 to Yoo discloses a process to selectively form silicide plates over source contacts in an SRAM process. A polysilicon layer is deposited overlying the SRAM polysilicon gates, sources, and drains. The polysilicon layer is removed except over the source or drain regions where silicide is planned. Titanium is deposited and heat-treated to form silicide. The excess titanium is then removed. U.S. Pat. No. 5,723,374 to Huang et al teaches a process to form stacked capacitor DRAM devices. Silicon nitride sidewall spacers are formed over the interpoly oxide to make it easier to remove the polysilicon bottom plate layer during the etch. U.S. Pat. No. 5,866,449 to Liaw et al discloses a process to fabricate a SRAM device. U.S. Pat. No. 5,661,085 to Teong teaches a process to form silicide contacts to source and drain regions. U.S. Pat. No. 5,340,774 to Yen teaches a process to form transistor contacts using local planarization. A fill layer of an insulator material is deposited and blanket etched to from planarizing fills between polysilicon lines. The fills are then etched away where contacts are desired.